Udemy - VLSI/FPGA Resume Project 2D DMA Controller with APB+AXI Inf

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Free Download Udemy - VLSI/FPGA Resume Project 2D DMA Controller with APB+AXI Inf
Published: 3/2025
Created by: SKY SiliconThink
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Level: Intermediate | Genre: eLearning | Language: English | Duration: 12 Lectures ( 2h 10m ) | Size: 1.1 GB

Final Kick of Goal at Interview
What you'll learn
Concept of DMA Operation
Design Spec. of this 2D DMA Controller
Hardware Architecture Analysis
Learn to Design Complex IP by Youself
RTL Code Walkthrough
Behavior Model of AXI Slave and APB Master
Complex IP Verificaiton Enviroment
Complete Zynq FPGA Project that Implement Plants Vs. Zombizes Game Using this IP Designed by Yourself
Requirements
Digital Fundamental
Verilog
APB3/AXI4 Bus Protocol
Description
In this course, you'll design a useful and complex IP block named as 2D DMA controller. For design part, it may take about 2000+ lines of Verilog code. I will also give an application example of this IP blocks: the Plants Vs. Zombies 2D game on zynq7010 FPGA platform. Using this powerful DMA block, actually you can make any 2D games. This's just effort of software.If you follow me to finish this project, it must be a big plus that can make your stand out from other candidates. And you can learn to design other complex IP blocks.1~5 enrollment: 80% discount;6~10 enrollment: 70% discount;11~20 enrollment: 60% discount;21~30 enrollment: 50% discount;31~40 enrollment: 40% discount;41~50 enrollment: 30% discount;51~99 enrollment: 25% discount;Please contact the instructor for coupon of discount.It' a rich feature 2D DMA controller with APB3+AXI4 interface. It's specially designed for image/video application, while compatible with traditional 1D DMA controller. Here are the main features (should be competitive with DMA IP from ARM or Synopsys):1) source/destination address can start from any byte location (no need 32bit aligned);2) Support data copy of 2D window with data length in each dimension is[y_size, x_size];3) Value range for x_size is[4, 65536];4) Value range for y_size is[1, 65536];5) There can be any number of byte gap after each line of x_size byte; And the gap for source/destination can be different;6) Support scatter-gather mode (command linked list); Once started by SW, it can copy at most 256 blocks of 2D window;7) Utilize some advanced feature to AXI bus protocol to improve data bandwidth: read cmd outstanding, read date out-of-order, concurrency of read/write on AXI interface;Any Tech. problem, you can drop your question in a discussion group, using slack APP. Please check the introduction section for detailed Info. about technic support.Wish you can find a decent job in VLSI/FPGA design.
Who this course is for
Graduate Student Who Wants to Seek a Job in VLSI/FPGA Design
Engineers Who Wants to Improve VLSI/FPGA Design Skill
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